2 nm Chips & High-NA EUV
Gate-all-around 2 nm chips are in volume production since late 2025; High-NA EUV, the next lithography step, starts with Intel’s 14A (risk production 2027).
Open in the interactive tree →In nanosheet transistors the gate wraps around the channel on all sides, and some processes also deliver power from the back of the chip. High-NA EUV (numerical aperture 0.55) exposes finer structures in a single step, but each machine costs hundreds of millions of euros. The name “2 nm” is a marketing label, not a physical feature size.
As of now
TSMC says its N2 process (nanosheet transistors) started volume production in Q4 2025, with N2P due in H2 2026; its A16 process with backside power slipped to 2027, A14 is targeted for 2028, and A13 and A12 (2029) are not expected to need High-NA EUV. Intel launched Panther Lake (Core Ultra Series 3, unveiled at CES on 5 January 2026), its first 18A chip with RibbonFET and PowerVia. ASML’s first production-grade High-NA scanner, the EXE:5200B (175 wafers per hour, 0.7 nm overlay), has passed acceptance testing at Intel, which plans risk production of 14A in 2027.
Open steps
- Defect-free thin resists for High-NA Medium AI leverageAt 0.55 NA the resist must be thinner, which raises line roughness and random bridge and break defects; new resists and etch steps must make them rare enough for yield.
- Full-chip inverse lithography High AI leverageHigh-NA masks benefit from curvilinear, 3D-aware optical correction; computing it for a whole chip is slow and sets how fast new designs reach the fab.
- Yield learning for backside power Medium AI leverageChips that deliver power from the back need wafer bonding, thinning and tiny through-silicon vias; defects there decide cost and ramp speed of A16-class processes.
Where AI could help
Medium AI leverage. AI speeds mask and process computation and defect analysis, but scanners, resists and fab ramps set the schedule.
- GPU-accelerated inverse lithography and mask proximity correction
- Machine-learned resist and stochastic-defect models to widen High-NA process windows
- Defect inspection and yield learning across fab data
- Recipe optimization with Bayesian search on pilot lines
Shown so far
- In March 2023 NVIDIA said (company claim) its cuLitho library speeds up computational lithography by up to 40 times on GPUs, with TSMC, ASML and Synopsys integrating it. source
Prerequisites
- Abbe's Image Theory (Zeiss)1873Resolution scales with wavelength over numerical aperture; High-NA raises NA
- Moore's Law1965
- Foundry Model (TSMC)1987Foundry customers pooled the demand that pays for each new node, 2 nm included
- Immersion Lithography2003Raising numerical aperture was already the lever used in immersion lithography
- EUV Lithography2019